In many FPGA applications it is required to provide the option for registering the incoming and outgoing signals to and from the FPGA. For this purpose IO cells are usually designed to include flip-flops. A flip-flop is provided with the output buffer to register the signal coming from the core, before going to the IO pad, and with the input buffer to register the signal coming from the pad, before going to the core. Sometimes the tri-stating signal of the output buffer is also provided with a flip-flop for synchronization. These IO Blocks (IOB) include the option to use these flip-flops or to bypass them depending upon the type of application. This is described in, e.g., Xilinx's data book of year 1999 (Virtex device IOB on page 3–6), which is incorporated by reference.
In applications where registered inputs-outputs are not required, there is direct signaling between IO pads and core and the flip-flops are left unutilized. It is also possible that some of IOs of the FPGA device are not used, and in this case flip-flops associated with these IOs are also not utilized. With minimal addition of hardware, these flip-flops can be utilized for some other purpose thereby reducing the load on internal core Logic cells.
U.S. Pat. No. 5,869,982, which is incorporated by reference describes an apparatus and method for interconnecting adjacent unused IO pad circuitry to provide independent logic function. The invention described in the '982 patent does not, however, provide for the connection of such unused circuitry to the core logic, nor does it utilize the unused circuit elements of the Look Up Tables.